What (who) is bus Arbiter - definition

SYSTEM FOR MULTIPLE BUS ACCESS

Bus Master; Bus master; First party DMA; Bus arbiter; Bus arbitration; First-party DMA

First Party DMA

Bus mastering

In computing, bus mastering is a feature supported by many bus architectures that enables a device connected to the bus to initiate direct memory access (DMA) transactions. It is also referred to as first-party DMA, in contrast with third-party DMA where a system DMA controller actually does the transfer.

https://en.wikipedia.org/wiki/Bus_mastering

bus master

<architecture> The device in a computer which is driving the address bus and bus control signals at some point in time. In a simple architecture only the (single) CPU can be bus master but this means that all communications between ("slave") I/O devices must involve the CPU. More sophisticated architectures allow other capable devices (or multiple CPUs) to take turns at controling the bus. This allows, for example, a network controller card to access a disk controller directly while the CPU performs other tasks which do not require the bus, e.g. fetching code from its cache. Note that any device can drive data onto the data bus when the CPU reads from that device, but only the bus master drives the address bus and control signals. Direct Memory Access is a simple form of bus mastering where the I/O device is set up by the CPU to read from or write to one or more contiguous blocks of memory and then signal to the CPU when it has done so. Full bus mastering (or "First Party DMA", "bus mastering DMA") implies that the I/O device is capable of performing more complex sequences of operations without CPU intervention (e.g. servicing a complete NFS request). This will normally mean that the I/O device contains its own processor or microcontroller. See also distributed kernel. (1996-08-26)

Wikipedia

Bus mastering

In computing, bus mastering is a feature supported by many bus architectures that enables a device connected to the bus to initiate direct memory access (DMA) transactions. It is also referred to as first-party DMA, in contrast with third-party DMA where a system DMA controller actually does the transfer.

Some types of buses allow only one device (typically the CPU, or its proxy) to initiate transactions. Most modern bus architectures, such as PCI, allow multiple devices to bus master because it significantly improves performance for general-purpose operating systems. Some real-time operating systems prohibit peripherals from becoming bus masters, because the scheduler can no longer arbitrate for the bus and hence cannot provide deterministic latency.

While bus mastering theoretically allows one peripheral device to directly communicate with another, in practice almost all peripherals master the bus exclusively to perform DMA to main memory.

If multiple devices are able to master the bus, there needs to be a bus arbitration scheme to prevent multiple devices attempting to drive the bus simultaneously. A number of different schemes are used for this; for example SCSI has a fixed priority for each SCSI ID. PCI does not specify the algorithm to use, leaving it up to the implementation to set priorities.

https://en.wikipedia.org/wiki/Bus mastering